1. Field of Invention
The present invention relates to a method of removing thin film layers in a semiconductor component for failure analysis. More particularly, the present invention relates to a method of removing thin film layers in a semiconductor component using a focused ion beam (FIB).
2. Description of Related Art
A semiconductor component is composed of a number of thin film layers. Manufactured semiconductor components will normally go through a series of tests. Sometimes, a faulty semiconductor component is found through the testing, and a failure analysis needs to be carried out to find the root cause of the problem. To perform a failure analysis, all the thin film layers above the defective layer first have to be removed. For example, if there is a pin hole formation or a breakdown in the gate oxide layer of a MOS component, all the thin film layers above the gate oxide layer need to be removed to expose the defective gate oxide layer so that the component can be inspected. Therefore, how to remove the top thin film layers to reveal the defective thin film layer of a semiconductor component is a crucial step in failure analysis.
FIGS. 1A through 1C are a series of cross-sectional views showing the steps involved in removing all the thin film layers above a defective thin film layer of a semiconductor component according to a conventional method.
As shown in FIG. 1A, a silicon substrate 10 having at least a semiconductor component formed thereon is provided. The semiconductor component can be, for example, a MOS component 11 having a field oxide layer 12, a gate oxide layer 14, a gate terminal layer 15, source/drain terminals 16 and gate spacers 17. Furthermore, there are a multiple of interconnects, such as metallic layers 19 and 21, and insulating layers such as 18, 20 and 22, above the semiconductor component.
First, the semiconductor components above a wafer is electrically tested to check out the faulty component, for example, MOS component 11. Then, as shown in FIG. 1B, a mechanical polishing method is used to remove the metallic layers 19 and 21 and the insulating layers 18, 20 and 22 to expose the gate terminal layer 15. During polishing, the polishing end point are determined by visual inspection. As such, the process is difficult to control. Also, the polishing time is quite long, and requires roughly 2 hours.
Next, as shown in FIG. 1C, the gate terminal layer 15 is removed to expose the gate oxide layer 14 using potassium hydroxide (KOH) as the etching solution. Subsequently, a failure analysis is performed.
The above conventional method of removing the thin film layers has the following disadvantages, namely:
1. The time required to prepare the sample is quite long, because for every faulty component located, a test specimen has to be prepared. Subsequently, each sampled point requires roughly 2 hours of mechanical polishing time to remove all the thin film layers above the defective thin film layer.
2. Using a mechanical polishing method to control the residual thickness of a gate polysilicon layer is a complicated matter. Therefore, it is easy to get a failed sample. As such, the sampling success rate is small.
3. During specimen polishing, it is very difficult to keep the polishing machine absolutely horizontal and stable. As a result, when a sample point is ground to a suitable thickness, other parts of the test specimen may have been ground down to the silicon substrate, thus causing damage to other sampled points. Hence, only one sample point can be inspected for each test specimen using the mechanical polishing method.
In light of the foregoing, there is a need in the art for improving the method for removing the thin film layers above a defective thin film layer in a semiconductor component for failure analysis.